A. Technical Field
The present invention relates to a voltage generator, and more particularly, to systems, devices and methods of configuring a charge pump system by incorporating an auxiliary charge pump to generate an intermediate voltage that is used to boost up a primary charge pump according to a level of an input supply voltage. Such a charge pump based voltage generator is compatible to a wide input supply range, capable of sustaining a large output load and effectively reduces the chip estate.
B. Background of the Invention
A charge pump is widely applied in digital and analog electronics to provide a voltage that is beyond a range between its high and low supply voltages. For instance, in flash memory and light emitting diode (LED) drivers, the charge pump is coupled to receive an input supply voltage that may vary within a wide voltage range, and has to generate a supply voltage that has a fixed level that is higher than that of the supply voltage. This supply voltage is used to erase memory cells in the flash memory, or generate a desirable LED current to drive the LED drivers.
FIGURE. (“FIG.”) 1A illustrates a typical charge pump 100. Such a charge pump 100 is normally implemented as a DC to DC converter that uses capacitors as energy storage elements. The charge pump 100 alternates between periodic charging and discharging cycles. During a charging cycle, switches 102 and 104 are turned on, while switches 106 and 108 are disabled. A capacitor 110 is coupled between an input supply voltage VIN and the ground, and charged up to store a certain amount of electrical charges. During a subsequent discharging cycle, switches 106 and 108 are enabled, while switches 102 and 104 are switched off. Capacitor 110 is biased between the input supply voltage VIN and an output of the charge pump 100, and further coupled in series with a load capacitor 112 loaded at this output. The electrical charges previously stored in capacitor 110 are redistributed to the load capacitor 112, generating a charge pump (CP) output voltage VCPM.
Switches 102-108 may be implemented using a complementary metal-oxide-silicon (CMOS) analog switch, or particularly, a CMOS transmission gate 150 as illustrated in FIG. 1B. The switch 150 comprises a n-type MOS (NMOS) transistor and a p-type MOS (PMOS) transistor that are coupled in parallel. The transistor gates are respectively controlled by two complementary switch control signals SW_EN and SW_EN_. As a result, the switch 150 controls the connection between an input node IN and an output node OUT. The complementary switch control signals SW_EN and SW_EN_ are generated via an internal oscillator driven by the CP output VCP. Transistors used in switches 102-108 are selected according to the levels of the input supply voltage VIN and the CP output voltage VCP. For instance, when the input supply VIN is 3.6V, switches 102-108 are normally made of 3V PMOS and NMOS transistors.
A wide range for the input supply VIN is desirable for the charge pump 100, but many charge pumps cannot start properly when the input supply VIN is extended to a low level, e.g., less than 1.0V. Prior to reaching a desirable level, the CP output voltage VCPM has to be initially charged up to the level of the input supply VIN. During power up, PMOS transistors in switches 102-108 are controlled to enable the above alternating charging and discharging cycles, and due to the low levels of VIN and VCPM, the on-resistance of the analog switch 150 is normally relatively large. The charge pump may not sustain a sufficient current to drive an output load coupled at the charge pump output, and particularly, the startup process most probably fails when the output load is relatively large. Therefore, the CP output voltage VCPM is pulled down by the output load, rather than being charged up, due to the insufficient VIN level and the large load.
Even when the CP output voltage VCPM is successfully charged up, the efficiency of the charge pump 100 has to be compromised in order to maintain a small chip area. For higher operation efficiency, PMOS and NMOS transistors of larger size are desired, such that the equivalent resistance of the analog switches 102-108 is reduced and the drive current is enhanced to charge/discharge the load capacitor 112 efficiently. However, larger transistors are unavoidably associated with more chip area. When a smaller chip estate is demanded for a cost or power concern, more current is consumed to charge and discharge the gates of these larger transistors, and the efficiency of the charge pump 100 may have to be compromised in a conventional charge pump 100.
A better solution is needed to ensure a proper startup at a low input supply voltage, efficient operation, and a small chip estate in a voltage generator.